1. Field of the Invention
The present invention relates to a moving image coding apparatus for compressing and coding moving image data.
2. Description of the Related Art
A camera-integrated moving image recording apparatus (i.e., a digital video camera) is well known for compressing and coding captured moving image data of an object and recording the compressed and coded moving image data on a recording medium. Recently, a disk medium or semiconductor memory which offers enhanced convenience as a recording medium (e.g., having a high random accessibility) is gradually replacing conventional magnetic tape media. However, such random access media generally have less recording capacity compared to that of the tape media, therefore, there is a need for highly efficient compression coding of the moving image data.
Furthermore, as public expectations grow for high image quality, a digital video camera that handles a high-definition (HD) video data containing a greater amount of information has been produced. Accordingly, highly efficient compression coding is required to compactly recording a high-quality moving image data.
As moving image compression method, the moving picture experts group (MPEG) methods (i.e., MPEG-2 and MPEG-4) have been developed, which are followed by development of H.264 standard having a higher compression rate. The H.264 standard requires a larger calculation amount in coding or decoding than the conventional coding methods such as MPEG-2 and MPEG-4, however, the H.264 standard can realize high coding efficiency.
One method to increase the coding efficiency in the H.264 standard is macro block partitions. This is a technique to finely divide a macro block (a coding block) which is a unit of the coding to form macro block partitions (motion compensation blocks) in order to perform motion compensation in a motion compensation block unit. In this way, more precise motion compensation can be achieved.
Against the backdrop as described above, a bus rate demanded to a frame memory which is provided in the moving image coding apparatus becomes extremely high due to an increase in the amount of information of the moving image for coding and segmentation of the motion compensation blocks. The frame memory refers to a memory for storing image data used particularly in coding.
Japanese Patent Application Laid-Open No. 8-123953 discusses a storing method of pixel data on the frame memory. More specifically, consecutive pieces of pixel data in one direction on a screen are stored as one word for one address of the frame memory. Further, consecutive addresses of the frame memory are arranged in a direction perpendicular to the above direction of the consecutive pieces of pixel data stored as one word. In a typical dynamic random access memory (DRAM), consecutive access without overhead is possible in a row address direction within a specific range. A high-speed memory access is realized by using this feature.
Recently, a bus width of the frame memory is being widened to increase a bus rate of the frame memory. When the motion compensation block is segmented, pixels stored on one address of the frame memory become more in number than horizontal pixels of the motion compensation block. Consequently, according to the method discussed in Japanese Patent Application Laid-Open No. 8-123953, a chance of accessing unnecessary pixel data is increased, and memory access efficiency is degraded.